Developing a concept to convert LD/STL to VHDL

Abstract

A Programmable Logic Controller (PLC) is a microprocessor based solid state device which is a very significant control component unit in industrial automation systems. Ladder diagram (LD) is a form of graphical language type PLC programming. LDs and Statement Lists (STL) are used to program PLCs. Both of these programming methods represent the schematics of electrical relay circuit diagram. Since LD programs are executed in a sequential and cyclic way, the operational efficiency and performance of PLC will be limited by the length of the ladder diagram and the operational speed of the microprocessor. Field Programmable Gate Array (FPGA) is a new technology used in industrial process control systems. VHDL (VHSIC-HDL- Very High Speed Integrated Circuit - Hardware Description Language) programming is used to program FPGA devices. Because of its parallel execution system and reconfigurable hardware structure, FPGA has excellent performance. Therefore, flexible and high speed systems can be implemented using FPGA. The main aspect of this research was to develop a concept to convert LD/STL to VHDL. By using Siemens - STEP 7 Micro/WIN - version 4.0.81 and Xilinx® – ISE Design Suite version 14.6 software, this concept was developed to convert Bit Logic LDs into VHDL. After identifying the Boolean logic of the STL code, inputs and outputs are declared in the entity part and PLC to FPGA conversion logic is defined in the architecture part of the VHDL code. To overcome the performance limitations of microprocessor based PLCs, FPGA based PLC implementation is suggested as a better approach.